A vertical power diode typically comprises a low n− doped base layer, a high n+ doped cathode layer on one side of the base layer and a high p+ doped anode layer on the other side of the base layer. The anode and cathode layers are typically formed by implantation and a subsequent diffusion of dopants into an n− doped substrate (wafer). On their outer side the cathode layer and the anode layer are covered with metal layers for electrically contacting the diode. The cathode diffusion and metallization normally extend to the physical edge of the device. The anode diffusion, on the other hand, has to be terminated at some distance from the edge in order to be able to support an electric field when reverse biased. Normally, this is done by limiting the p+ doped anode layer to the central part of the diode and surrounding it by a field-limiting junction termination. The anode metallization thereby has about the same size as the p+ doped anode layer itself. The area between the p+ doped anode layer and the n+ doped cathode layer is normally defined as the active area of the diode.
A typical application for such a power diode is as a free-wheeling diode in an IGBT inverter circuit. In such an application, the critical part of the diode operation appears when the diode is switched-off from the conducting on-state to the blocking off-state as the IGBT is switched on.
When the diode is forward biased, the anode will inject holes and the cathode will inject electrons into the n− base layer. In this way, an electron-hole plasma will be built up and stored in the n− base layer during the on-state phase. Due to the fact that the p+ doped anode layer is smaller in the lateral direction than the n+ doped cathode layer, a significant electron-hole plasma will thereby also be stored in the n− base layer underneath the anode junction-termination area. When the IGBT is switched on, the diode current will start decreasing with a current change diF/dt, determined by the switching speed of the IGBT. Due to the carriers stored in the n− base layer, the pn-junction is, however, not capable of supporting a reverse voltage right away. Eventually, the diode current will therefore reach zero and continue to increasingly negative values. At this stage, the stored holes will start flowing back to the anode and the stored electrons into the cathode contacts. After some time the pn-junction will be free of stored carriers and an electric field will start forming, supporting an ever increasing reverse voltage as the stored electron-hole plasma further gets swept out. Holes stored in the area of the n− base layer underneath the junction-termination will mainly flow into the edge of the p+ anode layer. Due to the curvature of the diffusion profile, the electric field will evidently be higher at this point than in the central part of the anode where 1D conditions prevail, i.e. the electric field in the central part has no component in the lateral direction. Especially during fast switch-off processes comprising high current changes diF/dts, the hole current density can be very high and thereby act as an additional positive space charge. This additional charge will further increase the electric field strength at the anode edge. If the electric field exceeds the critical strength, avalanche generation will set in (dynamic avalanche effect), and a further increase in current density will result. The combination of a high current density and a high electric field will lead to high power dissipation in this region. This can lead to a local thermal runaway and subsequent failure of the diode. In case of high IGBT switching speed, i.e. large current change diF/dt, high DC-link voltage, high circuit stray inductance, high initial diode forward current and a high diode temperature the situation will become more critical, and therefore, the probability of failure of the diode will rise.
DE 198 04 580 shows different embodiments of a power semiconductor diode by which such a before mentioned edge failure effect can be avoided. The proposed methods can be divided into two fundamentally different categories: Either the edge of the anode layer can be made less sensitive to the hole current using different termination methods or alternatively, the hole current can be eliminated. In one embodiment the anode layer comprises a p+ highly doped central region, which is surrounded by an outer region of the diode with a lower dopant concentration (p− doped). In this case, the emitter efficiency of the edge region of the anode will be smaller and therefore less electron-hole plasma will be stored underneath the junction termination area, thus reducing the dynamic avalanche effect during diode turn-off. Alternatively, a non-planar junction termination technique can be used, where the anode layer undergoes an etching process, leaving a mesa-like p+ doped central region with the contact metal placed on top the mesa. Additionally, in another embodiment the n+ doped cathode layer extends only in a central part of the diode and is surrounded by an n doped layer. Alternatively, it is also possible to restrict the cathode metal layer to the central part of the diode. In both cases, the electron emitting area on the cathode side is going to be reduced laterally. The current flow in the outer regions of the diode will be reduced and less charge will be stored there, again reducing the flow of holes into the edge of the anode junction during reverse recovery.
In DE 103 30 571 a vertical diode is shown. The diode has a cathode layer, which is surrounded by a low doped n− contact area at the edge. By such a cathode the injection of electrons will be extremely reduced, but cannot be completely eliminated.
The document EP 0 485 059 shows a power diode with a highly doped n++ layer on the cathode side. Outside the active area, highly doped p++ zones are embedded in the n++ layer so that the n++ and p++ zones alternate, the widths of these zones being equal to each other. An n+ doped buffer layer covers the p++ zones as well as the n++ layer. The p++ zones and the n++ zones are in contact with the cathode electrode, which covers the complete surface of the diode on the cathode side. As in this device p++ zones are alternating with n++ zones on the cathode side, carrier injection is reduced from the region outside the active area, but there are still carriers, which can be injected from this region.
U.S. Pat. No. 4,377,816 relates to an avalanche diode with p+ zones surrounding an n+ layer. The p+ zones are arranged in a distance to the n+ layer and the p+ zones are arranged directly adjacent to the n− doped base layer. The metallization on the cathode side covers only the central part of the device below the n+ layer, because otherwise the carriers would flow over the n− doped base layer directly to the cathode electrode, thus the effect of the n+ doped layer would get lost and the maximum field strength would be reduced. Furthermore, for the manufacturing of the cathode metallization an additional masking step is necessary.
FR 1 490 051 and EP 0 794 578 show a diode with p+ islands which are arranged on the cathode side within the n+ layer in the active region in order to inject holes during recovery, thus improving diode recovery softness.